1. Field of the Invention
The present invention relates to a semiconductor integrated circuit (IC) device, more particularly, to a semiconductor IC device of the gate array type fabricated with complementary metal insulator semiconductor (CMIS) transistors.
2. Description of the Related Art
The recent increase in the scale of integration of IC's and the change in user needs to small-lots of large scale integrated (LSI) semiconductor devices have led to increased emphasis on the so-called masterslice LSI semiconductor device as a means of reducing manufacturing costs and manufacturing time.
In a masterslice semiconductor device, as is well known, many basic element sets are formed in a semiconductor chip prior to determining the function to be performed by the chip. Each basic element set is fabricated with typical transistors, resistors, and so on to form a basic circuit (hereinafter referred to as a basic cell). Up to this point, the masterslice semiconductor device is mass produced in large quantities. Interconnecting lines are then formed between the basic cells and in each basic cell using a specified mask to obtain an LSI semiconductor device with the desired functional circuits.
This technique enables significant reductions in both design and manufacturing time since one need only design and fabricate the specified masks when manufacturing a new LSI semiconductor device. Furthermore, in a masterslice semiconductor device, since a large number of basic cells are regularly arranged in both the column and row directions on the semiconductor substrate and form a standardized matrix pattern, it is very easy to employ so-called computer aided automatic wiring for forming the interconnecting lines.
Such a standarized matrix pattern is usually called a "gate array". Of the different types of gate arrays, a CMIS gate array is most widely used for LSI semiconductor devices. Each of the basic cells of such an array includes CMIS transistors. CMIS transistors have the advantage of low-power operation and, therefore, a higher degree of integration of the LSI semiconductor device is possible.
CMIS gate array type LSI semiconductor devices, however, suffer from the problem of "latchup". In the latchup phenomenon, a parasitic silicon-controlled rectifier (SCR) is unwillingly created in the substrate. This SCR, when it remains on, can break the interconnecting lines and damage the basic cells.
in the prior art, latchup has been eliminated by forming n.sup.+ - and p.sup.+ -diffusion regions in the n-type silicon substrate and p-type well, for contact therewith, respectively. The n.sup.+ - and p.sup.+ -diffusion regions are formed between each two adjacent p-channel transistors of the basic cells and every two adjacent n-channel transistors of the basic cells, respectively. The insertion of n.sup.+ - and p.sup.+ -diffusion regions between every two adjacent basic cells impedes increases in the packing density of the basic cells and thus reduces the degree of integration of the device.